VLSI ARCHITECTURE-VLSI PROJECT
High-speed parallel Viterbi decoding: Algorithm and VLSI – architecture
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U IGITAL SIGNAL PROCESSING (DSP) APPLICA-tions often require computing speeds that cannot be achieved by standard signal processor implementations. In this case the use of customized dataflow processors is necessary to meet the given requirements. This requires
An efficient VLSI architecture and FPGA implementation of high-speed and low power 2-D DWT for (9, 7) wavelet filter
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This paper presents an efficient VLSI architecture of a high speed, low power 2-D Discrete Wavelet Transform computing. The proposed architecture , based on new and fast lifting scheme approach for (9, 7) filter in DWT, reduces the hardware complexity and memory
Stochastic mixed-signal VLSI architecture for high-dimensional kernel machines
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A mixed-signal paradigm is presented for high-resolution parallel innerproduct computation in very high dimensions, suitable for efficient implementation of kernels in image processing. At the core of the externally digital architecture is a high-density, low-power analog array
PIPE: A high performance VLSI architecture
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Albstract The PIPE architecture (Parallel lnstructions and Pipelined Execution) is proposed as a research vehicle for studying high performance VLSI architectures and organizations. Principal features are: 1) it is pipelined, 2) it is capable of a decoupled mode of operation
A digital VLSI architecture for real-world applications
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As the other chapters of this book show, the neural network model has significant advantages over traditional mcdels for certain applications. It has also expanded our understanding of biological neural networks b> providing a theoretical foundation and a set
A VLSI architecture for sound synthesis
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Sounds that come from physical sources are naturally represented by differential equations in time. Since there is a straight-forward correspondence between differential equation in time and nite difference equations, we can model musical instruments as simultaneous
VLSI Architecture of Fuzzy Logic Hardware Implementation: a Review.
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Abstract 1 A contributory paper on the study of VLSI architectures of various fuzzy processors and controllers designed for various applications is presented. The paper focuses on the study of VLSI implementation of fuzzy logic hardware to result in small silicon
A novel VLSI architecture for digital image compression using discrete cosine transform and quantization
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For multimedia and medical image transmission applications the data compression is an essential technique . Many data compression techniques have been proposed in the past But there is a scope to further improve such proposals. This paper in that direction
VLSI architecture for non-sequential inversion over GF (2m) using the euclidean algorithm
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This paper examines a VLSI implementation scheme of inversion over Finite Fields GF (2 m) based on the Euclidean algorithm. The multiplicative inverse can be used to perform division over finite fields. In contrast to previously published solutions, we developed a new logic
Parallel VLSI architecture and parallel interleaver design for low-latency MAP turbo decoders
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Standard VLSI implementation of turbo decoding requires substantial memory and incurs a long latency, which cannot be tolerated in some applications. A novel parallel VLSI architecture for low-latency turbo decoding is described, comprising multiple SISO elements
Reconfigurable VLSI architecture for FFT processor
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This paper presents a reusable intellectual property (IP) Coordinate Rotation Digital Computer (CORDIC)-based split-radix fast Fourier transform (FFT) core for orthogonal frequency division multiplexer (OFDM) systems, for example, Ultra Wide Band (UWB)
A minimum area VLSI architecture for O (logN) time sorting
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A generalization of a known class of parallel sorting algorithms is presented, together with a new architecture to execute them. A VLSI implementation is also proposed, and its area-time performance is discussed. It is shown that an algorithm in the class is executable in O (logn)
An Efficient VLSI Architecture for MC Interpolation in AVC Video Coding.
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ABSTRACT Advance Video Coding (AVC) has employed a 6-tap interpolation FIR filter in its motion compensation (MC) part for high coding efficiency. But it is accompanied by increasing the complexity in calculation and the number of memory access. And this
High throughput and cost efficient VLSI architecture of integer motion estimation for H. 264/AVC
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Variable block size motion estimation (VBS-ME) is one of the contributors to H. 264/AVCs excellent coding efficiency. Due to its high computational complexity, however, VBS-ME needs acceleration for real-time high-resolution applications. This paper proposes a high
Low power opportunities for a SIMD VLSI architecture incorporating integrated optoelectronic devices
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Integrated optoelectronic interconnect offers a potentially lower cost, higher density alternative to wire-based technologies for I/O. For most applications, low cost IC packages provide an effective means of I/O in a system. However, some applications, such as image
A Low-Cost Parallel VLSI Architecture for Low-Level Vision.
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ABSTRACT 111 this work a nlassively parallel VLSI architecture is discussed: PAPRICA, a mesh connected machine that can also simulate a pyramidal architecture . Its computational paradigm is based on the lnatchiug operator as defined in nlathematical morphology. This
3D discrete wavelet transform VLSI architecture for image processing
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In this paper, we propose an improved version of lifting based 3D Discrete Wavelet Transform (DWT) VLSI architecture which uses bi-orthogonal 9/7 filter processing. This is implemented in FPGA by using VHDL codes. The lifting based DWT architecture has the
A vlsi -oriented architecture for real-time raster display of shaded polygons
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This paper describes the organization of a large-scale graphics hardware system which can produce color, shaded, anti-aliased, perspective images of complex three-dimensional scenes in real time. By complex scenes we mean those consisting of at least 25,000
An Efficient VLSI Architecture for 3D DWT Using Lifting Scheme
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The role of the compression is to reduce bandwidth requirements for transmission memory requirements for storage of all forms of data as it would not be practical to put images, audio, video alone on websites without compression. The medical community has many
New VLSI architecture for motion estimation algorithm
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This paper presents an efficient VLSI architecture design to achieve real time video processing using Full-Search Block Matching (FSBM) algorithm. The design employs parallel bank architecture with minimum latency, maximum throughput, and full hardware