ADC With VCO-Based Integrator
A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $ DeltaSigma $ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13$ mu $ m CMOS FREE-DOWNLOAD [PDF] M Park… – Solid-State Circuits, research Journal of, 2009 Abstract—The use of a VCO-based integrator and quantizer within a continuous-time (CT) 16 analog-to-digital converter (ADC) structure is explored, and […]
SAR ADC architecture
SAR ADC architecture with digital error correction FREE-DOWNLOAD [PDF] M Hotta, M Kawakami, H Kobayashi… – … on Electrical and …, 2010 This paper describes a high-performance successive approximation register (SAR) analog to digital converter (ADC) using three comparators operating in parallel, instead of just one as in conventional ADCs. This comparator redundancy enables potentially faster operation,
adc-based feed-forward cdr
A 5-gb/s adc-based feed-forward cdr in 65 nm cmos FREE-DOWNLOAD [PDF] O Tyshchenko, A Sheikholeslami… – Solid-State Circuits, …, 2010 Abstract—This paper presents an ADC-based CDR that blindly samples the received signal at twice the data rate and uses these samples to directly estimate the locations of zero crossings for the purpose of clock and data recovery. We […]