Flash ADC
Design of a Low Power, Variable-Resolution Flash ADC FREE-DOWNLOAD [PDF] S Veeramachanen, AM Kumar… – … Conference on VLSI …, 2009 Abstract: In this paper, a low power and variable resolution (adaptive) flash ADC is proposed. The ADC enables exponential power reduction while the reduction in resolution is linear. In the proposed design, unused parallel voltage comparators are switched […]
synchronous ADC
A 20MS/s 5.6 mW 6b Asynchronous ADC in 0.6µm CMOS FREE-DOWNLOAD [PDF] T Tulabandhula… – | 2009 22nd International Conference on …, 2009 The design of an N-comparator based asynchronous Successive Approximation Analog-to-Digital Converter (SAR ADC) is described (with N = 6) working at 20 MS/s and consuming only 5.6 mW for low power high speed applications like […]
performance estimation for ADC
INL based dynamic performance estimation for ADC BIST FREE-DOWNLOAD [PDF] J Duan… – … and Systems (ISCAS), Proceedings of 2010 Abstract—Data acquisition time and accurate instrumentation are the most significant contributors to ADC test cost. For most ADC products, static linearity (INL/DNL) test is required. This paper presents a methodology for estimating an ADC’s dynamic performance from its tested INL