Power-delay optimization
Power-delay optimization in VLSI microprocessors by wire spacing FREE-DOWNLOAD [PDF] K Moiseev, A Kolodny… – ACM Transactions on Design …, 2009 Intel Corporation The problem of optimal space allocation among interconnect wires in a VLSI layout, in order to minimize the switching power consumption and the average signal delay, is addressed in this article. We define
VLSI architecture
High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm FREE-DOWNLOAD [PDF] Y Sun… – Proceedings of the 19th ACM Great Lakes …, 2009
vlsi layout-6
A new parallel algorithm for minimum spanning tree problem FREE-DOWNLOAD [PDF] R Setia, A Nedunchezhian… – … International Conference on …, 2009 ABSTRACT Minimum Spanning Tree (MST) is one of the well known classical graph problems. It has many applications in VLSI layout and routing, wireless communication and various other fields. In this paper, we