low power LDPC decode
Scalable and low power LDPC decoder design using high level algorithmic synthesis FREE-DOWNLOAD [PDF] Y Sun, JR Cavallaro… – SOC Conference, 2009. SOCC …, The VLSI layout view of this decoder with a core area of 1.2 mm2 (standard cells + SRAMs) is shown in Fig. R Memory (SRAM) P Memory (SRAM) Fig. 9. VLSI layout view of […]
vlsi layout-3
On exact solutions to the Euclidean bottleneck Steiner tree problem FREE-DOWNLOAD [PDF] SW Bae, C Lee… – Information Processing Letters, 2010 tree where the maximum of the edge lengths is minimized and the Steiner points in the resulting tree can be chosen in the whole plane R 2 . The classical and the bottleneck Steiner tree […]
vlsi layout-2
A spectral algorithm for improving graph partitions FREE-DOWNLOAD [PDF] MW Mahoney, L Orecchia 2009 the degrees of the vertices in the set S. Interest in this problem derives both from its numerous practical applications, such as image segmentation, VLSI layout and clustering (see the survey of Shmoys [Shm97]), and from its theoretical connections to areas such as […]