capacitance sensitivity
Implementation of algorithms to determine the capacitance sensitivity of interconnect parasitics in the Magic VLSI layout tool FREE-DOWNLOAD [PDF] NKH Huang – 2009 Capacitance Sensitivity of Interconnect Parasitics in the Magic VLSI Layout Tool by Nick Kuan-Hsiang Huang A new set of capacitance models is imple- mented in the Magic VLSI layout tool to improve the capacitance accuracy based […]
vlsi layout-1
A lower bound for the tree-width of planar graphs with vital linkages FREE-DOWNLOAD [PDF] I Adler 2010 It is a classic problem in algorithmic graph theory and it has many applications, eg in routing problems, PCB design and VLSI layout It is NP-hard and it remains NP-hard on planar graphs [10]. Node-disjoint paths on the mesh and […]
Polygons from VLSI Layouts
Fast Continuous Haar and Fourier Transforms of Rectilinear Polygons from VLSI Layouts FREE-DOWNLOAD [PDF] R Scheibler, P Hurley… 2010 – avoid costly physical simulation by directly predicting the printability of the layouts using a classifier trained with feature vectors from orthogonal transforms. VLSI layout file sizes are expanding rapidly, with an in- creasing number of transistors packed […]