Timing-Driven Interconnect Synthesis
Timing-Driven Interconnect Synthesis FREE-DOWNLOAD [PDF] J Hu, G Robins… – 2009 Introduction In this chapter we address performance-driven interconnect synthesis, which seeks to optimize circuit performance by minimizing signal delays to critical sinks.
Device-level placement
Device-level placement for analog layout: an opportunity for non-slicing topological representations FREE-DOWNLOAD [PDF] F Balasa – … Automation Conference, 2001.Abstract- Layout design for analog circuits has historically been a time consuming, error-prone, man- ual task. Its complexity results not so much from the number of devices, as from the complex interac- tions among devices or with the operating environ- […]
Hierarchical extraction
Hierarchical extraction and verification of symmetry constraints for analog layout automation FREE-DOWNLOAD [PDF] S Bhattacharya, N Jangkrajarng… – 2004 Abstract – Device matching and layout symmetry are of utmost importance to high performance analog and RF circuits. In this paper, we present HiLSD, the first CAD tool for the automatic detection of layout symmetry between two or more devices […]